Regviz

Espressif Systems /ESP32-P4 /LEDC /INT_RAW

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INT_RAW

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/LEDC/INT_RAW#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMER0_OVF_INT_RAW)TIMER0_OVF_INT_RAW 0 (TIMER1_OVF_INT_RAW)TIMER1_OVF_INT_RAW 0 (TIMER2_OVF_INT_RAW)TIMER2_OVF_INT_RAW 0 (TIMER3_OVF_INT_RAW)TIMER3_OVF_INT_RAW 0 (DUTY_CHNG_END_CH0_INT_RAW)DUTY_CHNG_END_CH0_INT_RAW 0 (DUTY_CHNG_END_CH1_INT_RAW)DUTY_CHNG_END_CH1_INT_RAW 0 (DUTY_CHNG_END_CH2_INT_RAW)DUTY_CHNG_END_CH2_INT_RAW 0 (DUTY_CHNG_END_CH3_INT_RAW)DUTY_CHNG_END_CH3_INT_RAW 0 (DUTY_CHNG_END_CH4_INT_RAW)DUTY_CHNG_END_CH4_INT_RAW 0 (DUTY_CHNG_END_CH5_INT_RAW)DUTY_CHNG_END_CH5_INT_RAW 0 (DUTY_CHNG_END_CH6_INT_RAW)DUTY_CHNG_END_CH6_INT_RAW 0 (DUTY_CHNG_END_CH7_INT_RAW)DUTY_CHNG_END_CH7_INT_RAW 0 (OVF_CNT_CH0_INT_RAW)OVF_CNT_CH0_INT_RAW 0 (OVF_CNT_CH1_INT_RAW)OVF_CNT_CH1_INT_RAW 0 (OVF_CNT_CH2_INT_RAW)OVF_CNT_CH2_INT_RAW 0 (OVF_CNT_CH3_INT_RAW)OVF_CNT_CH3_INT_RAW 0 (OVF_CNT_CH4_INT_RAW)OVF_CNT_CH4_INT_RAW 0 (OVF_CNT_CH5_INT_RAW)OVF_CNT_CH5_INT_RAW 0 (OVF_CNT_CH6_INT_RAW)OVF_CNT_CH6_INT_RAW 0 (OVF_CNT_CH7_INT_RAW)OVF_CNT_CH7_INT_RAW

Description

Interrupt raw status register

Fields

TIMER0_OVF_INT_RAW

Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value.
TIMER1_OVF_INT_RAW

Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value.
TIMER2_OVF_INT_RAW

Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value.
TIMER3_OVF_INT_RAW

Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value.
DUTY_CHNG_END_CH0_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished.
DUTY_CHNG_END_CH1_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished.
DUTY_CHNG_END_CH2_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished.
DUTY_CHNG_END_CH3_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished.
DUTY_CHNG_END_CH4_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished.
DUTY_CHNG_END_CH5_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished.
DUTY_CHNG_END_CH6_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished.
DUTY_CHNG_END_CH7_INT_RAW

Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished.
OVF_CNT_CH0_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.
OVF_CNT_CH1_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.
OVF_CNT_CH2_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.
OVF_CNT_CH3_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.
OVF_CNT_CH4_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.
OVF_CNT_CH5_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.
OVF_CNT_CH6_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6.
OVF_CNT_CH7_INT_RAW

Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data